Bit width of base-less number

[dalance]

The bit width of base-less number is 32 bits.
This come from SystemVerilog, but it has some restrictions.

• Unnecessary bit width extension cause by small value like 0
• Large value over 32-bit can't be used

So, in this issue, we consider to define base-less number as arbitrary width number.
What translation is reasonable?
Is there any unexpected edge-case of bit width calculation scheme?

Refs: #2046 (comment)