Not detect multiple driver error

Currenlty, veryl compiler does not detect `multiple driver` error.
As a result, invalid SV is generated.

Example:

```systemverilog
module ModuleA {
  var a: logic;

  always_comb {
    a = 0;
  }
  always_comb {
    a = 1; // Illegal assignment but no error is reported
  }
}
```