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Description
Veryl reports mismatch_type error for the code below.
module ModuleA::<WIDTH: u32> {
let _a: logic<WIDTH> = 0 as WIDTH;
}�]8;;https://doc.veryl-lang.org/book/07_appendix/02_semantic_error.html#mismatch_type�\mismatch_type (link)�]8;;�\
💥 "WIDTH" is expected to "enum or union or struct", but it is "generic
│ parameter"
╭─[:2:33]
1 │ module ModuleA::<WIDTH: u32, TYPE: type> {
2 │ let _a: logic<WIDTH> = 0 as WIDTH;
· ──┬──
· ╰── Error location
3 │ let _b: TYPE = 0 as TYPE ;
╰────
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